Grant fosters innovation through high-tech research partnership

Computer engineering professors Jie Han and Bruce Cockburn with (middle) computer engineering graduate student Michael Shoniker. Han, Cockburn and fellow professor Witold Pedrycz have been awarded a $300,000 NSERC Strategic Grant to work with an industry partner to address challenges in designing and manufacturing integrated circuits.

Edmonton—A group of three U of A engineering professors is teaming up with a Canadian high-tech startup company to develop intelligent algorithms that help to ensure that integrated circuit designs will indeed produce working chips in the most advanced semiconductor technologies.  Before being approved for mass production, such designs must be demonstrated to work correctly in simulation despite the presence of random variations in electronic properties that are inevitable at the nanoscale even with the tightest quality control measures.

ECE professors Jie Han, Bruce Cockburn, Witold Pedrycz and industry partner Solido Design Automation Inc., are developing algorithms that guide the verification of integrated circuit operation under different process parameters and possible operating conditions.  It is important to minimize the number of different scenarios or “corners” that need to be considered in detail during circuit verification in accurate but time-consuming simulations.  In recent years integrated circuit technologies have become far more complex, increasing the number of design corners from dozens to over 1,000 or even tens of thousands, Han says.

“We’ll use the new algorithms to find the circumstances or conditions in which we get the worst-case scenario,” he said. “By identifying the worst-case scenario you are able to produce an integrated circuit that can handle everything—which is the best case.”

The intelligent search algorithms should provide more timely feedback to chip designers so that they can improve their designs to make them more robust against process variations.  Scenarios that are unlikely to cause problems can be identified and verified later, or verified faster but with less accuracy.

Process variations are becoming an increasingly serious problem for new technologies that rely on nano scale devices.  In the case of integrated circuit transistors, key transistor properties are controlled by the precise number and physical positioning of dopant atoms in the very small transistor channel region. 

“If every transistor you produce has a different number of dopant atoms, there will be fluctuations in the properties of these devices—the switching behaviour of the devices will be different; you’ll be unable to ensure that all devices will perform uniformly,” said Han. “In larger devices from previous generations it didn’t matter so much but at the nano scale this has a bigger impact and is harder to control.”

In addition to considering the effects of device parameter variations, the new algorithms must also consider inevitable variations in power supply voltage and operating temperature.

The team has recently been awarded a $300,000 Strategic Project Grant from the Natural Sciences and Engineering Research Council of Canada to address challenges in manufacturing integrated circuits.

Han emphasizes that this is a team project that crosses engineering disciplines.

“I could not do this work on my own,” he said, adding that the involvement of his ECE colleagues is essential to winning the NSERC grant and achieving the project’s technical goals.

Cockburn is “very knowledgeable in a broad category of research areas and is certainly a leading expert on the design of test circuitry,” he said, and Pedrycz, a highly recognized scholar who holds the Canada Research Chair in Computational Intelligence is “a world-class researcher on intelligent algorithms whose participation is instrumental in our success.”